The present invention relates generally to double error correcting systems in digital signal reproducing apparatuses, and more particularly to a double error correcting system in a digital signal reproducing apparatus, which is capable of correcting errors in two information vectors (information words) among a plurality of information vectors within one block, by use of few number of elements (correcting matrix data) of a correcting matrix, upon detection of two vector (word) errors within one block by using error pointers of adjacent codes during reproduction of digital signals which are transmitted in units of blocks.
Digital signal recording and/or reproducing systems have been recently developed for recording digital signals obtained by digitally modulating sound signals and the like by use of such modulation methods as pulse code modulation (PCM), onto magnetic tapes and discs, and reproducing the digital signals thus recorded. Magnetic recording and/or reproducing apparatuses (VTRs) and disc recording and/or reproducing apparatuses are used in the above recording and reproduction of digital signals, since the occupied bandwidth of the digital signals is wide, however, in this type of a high density recording and/or reproducing system, a plurality of errors are generated in the codes of the digital signals due to scratches and dust particles on the recording medium, dropout of information, jitter, noise, fluctuation in the reproduction level, interferences between codes, and the like. There are two kinds of errors introduced in the digital signal codes, mainly, random errors which are generated in a random manner, and burst errors which are generated in a burst manner, and various code correcting methods have been presented for each of the above kinds of errors.
In a conventional double error correcting system (a system for correcting errors of two or more words) using error pointers of adjacent codes, complex matrix operations are necessary upon correcting double errors. Accordingly, in this type of a conventional system, the elements of the matrices are calculated in advance and stored in a memory device such as a read-only-memory (ROM), and these elements of the matrices are read out and used upon necessity. However, when a ROM device is used, an address counter is required for selectively reading out of the information from the ROM device, and the circuit construction of the error correcting apparatus becomes complex. Furthermore, in a case where the number of elements (the number of bits in one word) in one vector is large, when the number of bits in one word is fourteen and the number of words of digital signals within one block is six, for example, the required minimum memory capacity of the ROM device becomes 980 (=14.times.14.times.5). However, since the memory capacity of most ROM devices is 2.sup.N (N is an integer greater than zero), a plurality of these ROM devices must be used, and the conventional devices were disadvatageous in that the cost of the error correcting apparatus became high.